@hackage / spirv-enum

SPIR-V enumerations generated from Khronos JSON.

Latest1.104.350.0

Changelog

Changelog for spirv-enum

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to the PVP.

1.104.350.0

Generated from SPIRV-Headers for Vulkan SDK 1.4.350.1.

Breaking

SPV_AMDX_shader_enqueue was reworked upstream; 4 pattern synonyms removed:

  • BuiltIn.CoalescedInputCountAMDX — 5021, value reused by RemainingRecursionLevelsAMDX
  • Op.OpFinalizeNodePayloadsAMDX — 5075, value reused by OpEnqueueNodePayloadsAMDX
  • Op.OpInitializeNodePayloadsAMDX — 5090, value reused by OpNodePayloadArrayLengthAMDX
  • StorageClass.NodeOutputPayloadAMDX — 5076, now unassigned
Added

8 new modules:

  • ComponentType — numeric component types for cooperative vectors/matrices (FP16/32/64, (un)signed int 8–64, packed int8, FP8 E4M3/E5M2)
  • FPEncoding — alternate float encodings (BFloat16, FP8 E4M3/E5M2)
  • CooperativeMatrixReduce (bits) — cooperative-matrix reduction modes (row / column / 2×2)
  • CooperativeVectorMatrixLayout — cooperative-vector matrix layouts (row/column major, inferencing/training optimal)
  • MatrixMultiplyAccumulateOperands (bits) — operand flags for INTEL subgroup matrix multiply-accumulate
  • TensorAddressingOperands (bits) — tensor addressing operands (tensor view, decode func)
  • TensorClampMode — tensor out-of-bounds clamp modes (constant / clamp-to-edge / repeat / repeat-mirrored)
  • TensorOperands (bits) — ARM tensor load/store operands (nontemporal, OOB value, availability/visibility, non-private)

369 new enumerants across existing modules: Op +189, Capability +76, Decoration +53, BuiltIn +13, LoopControl +10, ExecutionMode +8, ImageChannelDataType +7, StorageClass +4, GroupOperation +3, InitializationModeQualifier +2, FunctionControl +1, FunctionParameterAttribute +1, RayFlags +1, SourceLanguage +1 (Rust).

0.1.0.0

Initial release.

Generated from SPIRV-Headers for Vulkan SDK 1.3.290.0.