@hackage sv2v0.0.13.1

SystemVerilog to Verilog conversion

Categories
License
BSD-3-Clause
Maintainer
Zachary Snow <zach@zachjs.com>
Links
Versions
- 0.0.13.1 Mon, 23 Jun 2025
- 0.0.13 Thu, 20 Mar 2025
- 0.0.12 Tue, 7 May 2024
- 0.0.11 Thu, 22 Jun 2023
- 0.0.10 Sat, 23 Jul 2022
- 0.0.9 Sat, 2 Oct 2021

Installation
In your cabal file:
Dependencies (0)
- array >=0.5.3 && <0.6
- base >=4.12 && <4.20
- containers >=0.6.0.1 && <0.7
- directory >=1.3.3 && <1.4
- filepath >=1.4.2.1 && <1.5
- mtl >=2.2.2 && <2.4
Dependents (0)

A tool for coverting SystemVerilog to Verilog. Originally forked from the Verilog parser found at https://github.com/tomahawkins/verilog