@hackage hsverilog0.1.0

Synthesizable Verilog DSL supporting for multiple clock and reset

Categories
- Hardware
License
BSD-3-Clause
Maintainer
junji.hashimoto@gmail.com
Links
Versions
- 0.1.0 Thu, 19 Feb 2015

Installation
In your cabal file:
Dependencies (5)
- base >=4.6 && <5
- containers
- text
- transformers
- shakespeare
Dependents (1)
@hackage/acme-everything

Synthesizable Verilog DSL supporting for multiple clock and reset