@hackage / hsverilog

Synthesizable Verilog DSL supporting for multiple clock and reset

Latest0.1.0

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Last updated 19 Feb 2015, by junjihashimoto
License BSD-3-Clause
Categories Hardware
Maintained by: junji.hashimoto@gmail.com
Lottery factor: 0

Installation

Add this line in your cabal file

Readme

HsVerilog: Synthesizable Verilog DSL supporting for multiple clock and reset

Getting started

Install this from Hackage.

cabal update && cabal install hsverilog

Usage

Syntax is similar to Verilog. See tests/test.hs and following examples.

counter circuit

circuit "counter" $ do
  clk <- input "clk" Bit
  rstn <- input "rstn" Bit
  _ <- output "dout" $ 7><0
  reg "dout" (7><0) [Posedge clk,Negedge rstn] $ \dout ->
    If (Not (S rstn)) 0 $
      If (Eq dout 7) 
        0
        (dout + 1)

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